The present invention relates generally to the growth of heteroepitaxial layers on silicon (Si) substrates and, more particularly, to the use of micro- and nanoscale, 1-dimensional and 2-dimensional periodic and random structures generated on silicon and other substrates for forming compliant, thin films suitable for gettering defects and for accommodating lattice and thermal expansion mismatches during heteroepitaxial growth thereon.
Heteroepitaxial growth of pseudomorphic compound semiconductor films on silicon (Si) substrates has been a subject of enduring commercial interest due in part to applications in optoelectronics integrated circuits (See, e.g., O. Wada and J. Crow in Integrated Optoelectronics, edited by M. Dagenais et al., Academic Press (1995)), and low-cost, low-weight, high-efficiency solar cells having high mechanical strength (See, e.g., S. R. Messenger et al., 26th IEEE PVSC, 995 (1997)). High-quality heteroepitaxial growth on Si substrates beyond critical thickness hc is difficult to realize because of lattice constant and thermal expansion coefficient mismatches. For example, lattice expansion mismatch leads to misfit and threading dislocations resulting in a well-known crosshatch pattern for a SiGe layer system (See, e.g., Germanium-Silicon Strained Layers and Heterostructures, Suresh C. Jain, Advances in Electronics and Electron Physics, Supplement 24, Academic Press (1994)). Due to a large thermal expansion coefficient mismatch during for cooling after growth; that is, between 8.35xc3x9710xe2x88x926 and 5.9xc3x9710xe2x88x926 for germanium (Ge) and between 4.27xc3x9710xe2x88x926 and 2.57xc3x9710xe2x88x926 for Si (See, e.g., M. T. Currie et al., Appl. Phys. Lett. 72, 1718 (1998)), a high density of microcracks (See, e.g., B. G. Yacobi et al., Appl. Phys. Lett. 51, 2236 (1987)) and wafer bowing (See, e.g., S. Sakai, Appl. Phys. Lett. 51, 1069 (1987)) has been observed.
For these types of lattice and thermal expansion mismatched systems, the performance of minority carrier devices such as solar cells and laser diodes is degraded due to enhanced recombination at the lattice dislocations (See, e.g., P. M. Sieg et al., Appl. Phys. Lett. 73, 3111 (1998)), although moderately successful majority carrier devices have been reported (See, e.g., R. M. Sieg et al., J. Vac. Sci. Technol. B16, 1471 (1998)). Research directed to growth of high-quality (defect density  less than 105 cmxe2x88x922) heteroepitaxial films on Si substrates has been a field of active research for many years.
Several distinct approaches have evolved with varying levels of success:
One manner of eliminating, or reducing lattice and thermal mismatches is to form a xe2x80x9cvirtualxe2x80x9d substrate by growing a graded composition of the desired heteroepitaxial film on a defect-free Si substrate (See, e.g. D. J. Paul, Adv. Mater. 11, 191 (1999)). A layer having constant composition and the desired lattice parameter can then be grown on this buffer layer. By grading the composition, the misfit strain is distributed throughout the buffer layer thickness resulting in a three-dimensional misfit dislocation network. The primary objective of the constant composition layer is to achieve complete relaxation along with spatial separation from the underlying network of dislocations. Graded SiGe films have been prepared with low (between 105 and 106 cmxe2x88x922) defect densities (See, e.g., J. H. Li et al., J. Appl. Phys. 82, 2881 (1997)). However, several difficulties remain with this approach including surface roughness due to a pronounced  less than 110 greater than  crosshatch pattern that creates difficulties in lithographic patterning (See, e.g., M. A. Lutz et al., Appl. Phys. Lett. 66, 724 (1995)). Moreover, as the germanium concentration is increased, the crosshatch surface roughens further leading to an overlap of underlying strain fields, which tends to block threading dislocation glide and enhances dislocation pileups (See, e.g., S. B. Samavedam and E. A. Fitzgerald, J. Appl. Phys. 81, 3108 (1997)).
For GaAs on Si, similar approaches have been developed. A stress-balance approach based on GaAs1xe2x88x92x Px (See, e.g., A. Freundlich et al., Appl. Phys. Lett. 59, 3568 (1991)) and AlAs (See, e.g., J. D. Boeck et al., Appl. Phys. Lett. 59, 1179 (1991)) buffer layers has been investigated. An alternative approach is the application of strained layer super lattices of GaP/GaAsP and GaAsP/GaAs to relax lattice mismatch between GaP and GaAs (See, e.g., T. Soga et al., J. Cryst. Growth 77, 498 (1986)). However, there remain problems with a high-density of defects in thick GaAs films and in achieving single domain structure over the entire substrate due to thermal expansion coefficient mismatch between GaAs and Si. This results in stress and changes in lattice constant and band structure for GaAs grown on Si from those grown on GaAs substrates.
Mathews, et al., first proposed that limiting the lateral dimensions of the sample prior to growth could reduce the density of threading dislocations (See, e.g., J. W. Mathews et al., J. Appl. Phys. 41, 3800 (1970)). Subsequently, this approach has been extensively investigated for a wide range of material systems. Fitzgerald, et al. investigated misfit dislocations in growth of In0.05 Ga0.95 films on 2-xcexcm-high mesas having various lateral dimensions and geometries on (001) GaAs substrates (See, e.g., E. A. Fitzgerald et al., Appl. Phys. Lett. 52, 1496 (1988)). A reduction of linear interface dislocation density from about 5000/cm to approximately 800/cm for mesas as large as 100 xcexcm was demonstrated. Yamaguchi et al. in Appl. Phys. Lett. 56, 27 (1989) and E. A. Fitzgerald and N. Chand in J. Electron. Mat., 20, 839 (1991) later extended this approach to GaAs growth on patterned Si substrates. Yamaguchi, et al., teaches that the dislocation density of GaAs on Si is due to thermal stress, and that some stress relief is provided by the finite edges resulting in the reduction in dislocation density. Defect densities were reduced to approximately 1xc3x9710xe2x88x926 cmxe2x88x922 by a combination of thermal cycle annealing and lateral dimensions of about 10 xcexcm.
Defect densities have the potential of being reduced to  less than 105 cmxe2x88x922 by growth on substrates with finer lateral dimensions. The finite growth region can either be defined by vertical etching (See, e.g., E. A. Fitzgerald, J. Vac. Sci. Technol. B7, 782 (1989)), or use of an oxide mask (See, e.g., D. B. Noble et al., Appl. Phys. Lett. 56, 51 (1990)).
In modeling critical layer thickness, hc, of strained hetero layers on lattice mismatched nanostructured substrates, Luryi and Suhir determined that critical layer thickness increases sharply as finite seed areas are reduced (See, e.g., S. Luryi and E. Suhir, Appl. Phys. Lett. 49, 140 (1986)). According to this model, for Ge on Si, seed dimensions required are about 10 nm with a separation of approximately 3 nm, which eliminates most low-cost lithographic systems. Porous Si films support somewhat similar structures, and several growth studies were undertaken to evaluate model predictions. GaAs films grown on porous Si were found to contain a high density of microtwins and stacking faults originating from the roughness of the porous Si interface (See, e.g., Y. J. Mii et al., J. Vac. Sci. Technol. B6, 695 (1988)). GexSi1xe2x88x92x films grown on porous Si showed a predominance of 60xc2x0 dislocations with long misfit segments (See, e.g., Y. H. Xie and J. C. Bean, J. Vac. Sci. Technol. B8, 227 (1990)). In both cases, no reduction in either strain or dislocation density was observed when compared to growth on planar areas. This lack of agreement with the model may be attributed to the interconnected nature of porous Si structure as opposed to the isolated trenches assumed in the model.
An alternative model was later proposed by Lo (See, e.g., Y. H. Lo, Appl. Phys. Lett. 59, 3211 (1991)) based on the premise that strain is predominant in the epitaxial thin film, since the substrate is too thick to be compliant. In case of thin film substrate, the elastic energy between the epilayer and the substrate is more evenly distributed. Therefore, for the limiting case of a freestanding film, the strain energy is insufficient to generate misfit locations regardless of the epilayer thickness. According to Lo, growth is improved by two mechanisms: (a) increasing effective critical thickness; and (b) gettering of threading dislocations by freestanding thin films. An experimental verification of this approach was provided by Powell et al., for Si1xe2x88x92xGex growth on 50-nm-thick Si films in SOI configuration (See, e.g., A. R. Powell et al., Appl. Phys. Lett. 64, 1856 (1994)). Transmission electron microscope (TEM) measurements showed that for x=0.15 and SiGe layer thickness between 60 nm and 170 nm, no threading dislocations occurred in the SiGe layer; the underlying Si layer gettered all of the dislocations. Overall defect density was observed to be less than 105 cmxe2x88x922, and the Si layer was found to have about 108 cmxe2x88x922. However, in order to form thicker SiGe layers, or higher Ge concentration materials, Si thickness of approximately 10-nm thickness is required. This leads to the practical difficulty of the formation of thin (xcx9c5-10 nm) Si films. An alternative compliant approach has also been the focus recent work in which a single crystalline Strontium Titanium Oxide (STO) was used as a buffer layer between Si substrate and GaAs film (See, e.g., Epitaxial Growth by M. Meyer, Compound semiconductor, page 47, October (2001)). The STO film acts as a compliant layer, thereby reducing mechanical strain and thermal mismatch between substrate and GaAs epilayer.
Based on Lo et al., the experimental verification for thin films by Powell et al. and the work by M. Meyer, it appears that a compliant layer is a promising solution to resolving both the lattice and Thermal expansion mismatches.
The theory developed by Mathews, Stoica, Yamaguchi, and Fitzgerald, et al., teaches that the density of misfit dislocations is reduced by decreasing seed pad dimensions due to the strain relaxation and escape of dislocations at the edges. The compliant layer model proposed by Luryi and Suhir and supported by work by Meyer is a logical extension of these concepts to extreme nanoscale seed dimensions that are beyond the limit of most lithography systems. The compliant substrate developed by Lo requires a freestanding thin-film that is difficult to realize in practice. Zubia and Hersee combine aspects of 3D stress-relief mechanisms as proposed by Luryi and Suhir with Lo""s substrate compliance in SOI configuration (See, e.g., D. Zubia et al., Appl. Phys. Lett. 76, 858 (2000)). This model also predicts a significant relaxation of seed pad dimensions, from about 0.01 xcexcm to approximately 0.1 xcexcm. The patterned nanoscale islands in SOI configuration, although relatively compliant, have insufficient volume to absorb strain during growth of thick films. As growth fronts from nearest neighbors coalesce, defect density is significantly increased.
In pendeoepitaxy (PE) as taught by J. B. Kuang et al., Appl. Phys. Lett. 57, 1784 (1990), the vertical propagation of threading dislocations is blocked by using masks, while growth parameters are varied to enhance lateral growth, which is initiated on the sidewalls.
In facet-controlled epitaxial lateral growth as taught by Y. Honda et al., Jpn. J. Appl. Phys. 40, L309 (2001), vertical growth is encouraged until most of the threading dislocations are blocked, then lateral growth is enhanced leading to coalescence between growths from adjacent structures.
Accordingly, it is an object of the present invention to accommodate lattice and thermal expansion mismatches during growth of heteroepitaxial layers on suitable substrates.
Additional objects, advantages and novel features of the invention will be set forth, in part, in the description that follows, and, in part, will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the foregoing and other objects, and in accordance with its purposes of the present invention, as embodied and broadly described herein, the method for accommodating lattice and thermal expansion mismatches during heteroepitaxial growth hereof includes the steps of: forming a grating structure on the surface of a substrate; generating a readily etchable layer physically separating the grating structure from the substrate; and epitaxially growing the desired heteroepitaxial layer at least on the grating structure, whereby lattice and thermal expansion mismatches between the substrate and the epitaxially grown film are reduced.
In another aspect of the invention and accordance with its objects and purposes, the apparatus for growing heteroepitaxial materials hereof includes: a substrate having a substantially flat surface; and a grating structure formed on the surface of the substrate, the grating structure being physically separated from the substrate by a readily etchable layer, whereby epitaxial materials grown on the grating structure have reduced lattice and thermal expansion mismatches.
Benefits and advantages of the present invention include significant reduction of cost and enhanced performance for epilayer growth on lattice-mismatched material systems.